Note: The job is a remote job and is open to candidates in USA. K2 Space Corporation is building the largest and highest-power satellites ever flown. They are seeking a Senior ASIC Physical Design Engineer to implement advanced SoCs for next-generation satellite and space systems, working closely with various teams to achieve timing closure and optimize design integration.
Responsibilities
- Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification
- Perform timing closure and optimization across multiple corners and modes using industry-standard tools
- Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence
- Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment
- Develop and maintain scripts and automation to improve flow efficiency and consistency
- Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis
- Assist in chip-level integration, ECOs, and tapeout preparation
- Contribute to methodology development, tool evaluation, and flow documentation
- Support your product through production and spaceflight
Skills
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 5–10 years of experience in ASIC physical design for complex SoCs
- Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent)
- Strong understanding of timing analysis, power optimization, and physical verification flows
- Experience with hierarchical or flat SoC design methodologies
- Familiarity with FinFET technologies
- Working knowledge of DFT, UPF/CPF power intent, and ECO implementation
- Strong problem-solving skills and ability to work cross-functionally in fast-paced environments
- Exposure to radiation-hardened or space-qualified ASICs
- Experience with chip-package co-design or advanced packaging (2.5D/3D)
- Familiarity with physical design service vendor management or offshore collaboration
- Experience with sign-off through TSMC
- Experience with Gate-All-Around technologies
- Experience working in cross-functional, geographically distributed teams
Benefits
- Equity in the company
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Company Overview